1. Field of the Invention
The present invention relates to the system and method for handling a floating interruption in a information processing system with a multiprocessor configuration.
2. Description of the Related Art
FIG. 7 shows a conventional multiprocessor system configuration and is an example of a multiprocessor system configuration based on Futurebus+ prescribed by IEEE standard P896.1. FIG. 8 shows a conventional floating interruption handling system in a multiprocessor system.
Referring to FIG. 7, each processor 1 performs data processing and interruption handling. A main memory 2, storing instruction codes and data, can be shared by all the processors in the system. An external interruption controller 3 (which will be called an "ITC" hereinafter) issues a floating interruption request for all the processors. ITC 3 also issues additional information related to the request in response to a floating interruption acknowledgement notification by a processor 1. ITC 3 then clears the floating interruption request to be acknowledged by a processor 1, as part of a process of a floating interruption handling. A set of communication lines called common control lines 4 (which will be called a "Control Bus" hereinafter) transfer control information between the main memory 2 and a processor 1. Control Bus 4 also transfers control information of a floating interruption request from ITC 3 and of an acknowledgement notification of an interruption from a processor 1. A set of communication lines called common data lines 5 (which will be called a "Data Bus" hereinafter) transfer information between a processor 1 and the main memory 2. Data Bus 5 also transfers additional information related to a floating interruption request from ITC 3 in response to a floating interruption acknowledgement notification from a processor 1.
FIG. 8 shows a multiprocessor system configuration with floating interruption request lines individually and independently provided between a processor 1 and ITC 3. The numerals 1 to 5 in the figure correspond to those in FIG. 7.
A floating interruption handling system utilizes a generally known method of load-equalization among processors. It provides a high overall system efficiency in terms of throughput in a symmetrical-type multiprocessor system. This method adopts a priority scheme in which only one processor may announce the start of a floating interruption acknowledgement process in response to an interruption request from an Input/Output device. For instance, only if that one processor issues the announcement before any other processors, it can follow a floating interruption handling routine further.
The conventional floating interruption handling system will now be described with reference to FIG. 7. The process begins with an interruption request being issued by one or more Input/Output devices. The request is sent to the ITC 3 by the source or device via an interruption line (not shown). After identifying a floating interruption source, ITC 3 tries to gain the priority of exclusive access to Control Bus 4 and Data Bus 5 through use of a conventional bus arbitration technique. The conventional bus arbitration system or technique will not be discussed here since it is well known and is not essential to the present invention. When exclusive access is obtained, ITC 3 broadcasts a floating interruption request on Control Bus 4 and Data Bus 5 to all the processors in the system. When an interruption request signal on Control Bus 4 is detected by each processor 1, it processes the signal as a floating interruption request.
When the request is recognized by processor 1, it initially examines an internal condition for acknowledgement, for example, by the state of an interruption mask. When a processor 1 is determined to be in an "enabled state" after examination through the mask, it starts an acknowledgement process. When a processor 1 is determined to be in a "disabled state", it suspends the initiation of the acknowledgement process for a certain period and maintains such suspension until the condition changes to an "enabled state".
In accordance with the priority scheme implemented in the floating interruption handling method, a processor 1 which starts an acknowledgement process prior to others will initially follow an exclusive routine by announcing its start of an acknowledgement process on Control Bus 4. Upon receipt of such announcement, the other processors cancel their own internal acknowledgement processes, if such process is starting or pending. Here, however, there occurs a potential conflicting event. Specifically, two or more processors may start an acknowledgement process simultaneously when they detect a floating interruption request. They may, thereafter, try to issue a starting announcement simultaneously and spontaneously on Control Bus 4. This problem is caused where every processor 1 has an equal access to signals carried on the buses. A proposed solution is to implement a bus arbitration system which can decide which device in a system has priority in getting exclusive access to the buses. In this case, for instance, the system would determine which processor should use Control Bus 4. To be more specific, only one of processors can gain the priority of exclusive access to Control Bus 4 prior to others through a bus arbitration technique in which the processor 1 broadcasts its acknowledgement of a floating interruption on Control Bus 4. In response to the announcement, all the other processors, even those which tried to issue a starting announcement simultaneously, cancel their internal operations for the acknowledgement of a floating interruption, if executing or pending.
Following the starting announcement of a floating interruption acknowledgement process on the bus, the processor 1 provides its acknowledgement of a floating interruption to ITC 3 on Control Bus 4. In return, the processor receives additional information related to the present floating interruption request on Data Bus 5 from ITC 3. This terminates the whole process of floating interruption handling with regard to the processors 1.
ITC 3, in the meantime, clears the factor of acknowledged floating interruption. This will permit another request to be handled immediately after ITC 3 issues the additional information on Data Bus 5 in response to the acknowledgement notification from the processor 1 on Control Bus 4.
Conventionally, a floating interruption request is issued and controlled in the manner illustrated in FIG. 8. Referring to the figure, each processor outputs an individual wait status to ITC 3 for informing ITC 3 of its wait status, using the WAIT-0/WAIT-1 signal. Each processor 1 also has an individual floating interruption request input, receiving FINT-1 and FINT-0 signals, from ITC 3. When a floating interruption condition occurs in ITC 3, ITC 3 monitors both WAIT-0 and WAIT-1 signals from all configured processors, and then determines which processor is likely to handle a floating interruption within the minimum time. As a result, ITC 3 outputs the FINT-0 and/or FINT-1 signal(s) for a floating interruption request to the processor(s) which it has chosen. If a processor 1 is in the wait status and outputs the WAIT-i (i=0 or 1) signal, it means that a processor does not execute any process but just waits for interruption.
The following is how ITC 3 determines which processor 1 should serve a floating interruption request, given the current wait status of all of the processors:
(1) ITC 3 sends a floating interruption request to all the processors in a wait state.
(2) If ITC 3 detects no processor in a wait state, ITC 3 sends the request to all the processors in the system.
Further activity in the system of FIG. 8, such as a floating interruption acknowledgement process and its starting announcement, are performed by a processor 1, in the same manner as those stated herein with reference to FIG. 7.
As stated above, the devices in the multiprocessor system use the buses frequently for the various purposes in the conventional interruption handling system. A high frequency of bus use results in a critical problem for a floating interruption handling system, involving a poor performance when transferring information. There could be a serious information bottleneck, thereby degrading overall system efficiency in time and performance. To be more specific, Control Bus 4 and Data Bus 5 are used for each of the following purposes:
(1) information transfer between two or more processors and the main memory 2;
(2) broadcasting a floating interruption request by ITC 3;
(3) broadcasting the announcement of starting a floating interruption acknowledgement process by a processor 1; and,
(4) broadcasting the notification of a floating interruption acknowledgement for executing its acknowledgement process by a processor 1 for ITC 3.
Associated with such heavy bus use, there is yet another problem. When the buses are comparatively busy, reissuing a single floating interruption request using Control Bus 4 may not be desired when considering bus-use-efficiency. In order to avoid such a problem, a single use of a bus for a single purpose may be ideal for system efficiency. The application of this ideal method in the conventional system, however, leads to a waste factor. In other words, all the processors must receive a floating interruption request anyway, regardless of whether their internal conditions are ready for it or not, when a floating interruption request is issued on the bus. In this respect, extra hardware resources are needed in a processor 1 to receive a floating interruption request whenever ITC 3 issues such request. The extra hardware resources could be special additional circuits only for receiving the request whenever one is issued.
In the interruption handling system illustrated in FIG. 8, the individual installation of a wait status line and a floating interruption line between a processor 1 and ITC 3 for a single purpose, involves two aspects. One consideration is a positive feature, that is, a decreasing frequency of bus use. The other consideration is a negative feature, that is, increasing the number of signal lines and/or pins in the system. Better performance in handling a floating interruption is provided when the wait status lines are dedicated only for informing ITC 3 of the wait status of each processor 1. ITC 3, therefore, can easily decide which processor 1 to serve for a floating interruption, which is surely time-saving and contributes well to the achievement of a higher overall system efficiency. From an architectural point of view, however, the number of signal pins needed for those individual lines is another problem causing a fear of increasing the total number of lines and pins in the system. The matter is even worse when a processor 1 and ITC 3 are separately integrated in two or more LSIs or when the number of processors 1 is increased in a multiprocessor system.